In an integrated circuit, it is desirable for all transistors with the same designed transistor gate (gate) length to have the same performance. It has been found that transistor performance is dependent upon the environment surrounding the gate. For example, transistors with closely spaced (dense) gates have significantly different performance than transistors with isolated gates even though both are designed with the same gate width and length. Photo lithography effects during printing and micro-loading effects during etch contribute to the performance differences.
In order to minimize differences, dummy gates are placed next to isolated active gates so the isolated active gates appear to have an environment similar to dense gates during photolithography and during plasma etch. It is common to surround an isolated gate with multiple dummy gates and to place multiple dummy gates next to the outer most gate of a series of dense gates so all the gates have a similar environment during pattern and etch.